ATOCore/scripts/retrieval_eval_fixtures.json

[
  {
    "name": "p04-architecture-decision",
    "project": "p04-gigabit",
    "prompt": "what mirror architecture was selected for GigaBIT M1 and why",
    "expect_present": [
      "--- Trusted Project State ---",
      "Option B",
      "conical",
      "--- Project Memories ---"
    ],
    "expect_absent": [
      "p06-polisher",
      "folded-beam"
    ],
    "notes": "Canonical p04 decision — should surface both Trusted Project State (selected_mirror_architecture) and the project-memory band with the Option B memory"
  },
  {
    "name": "p04-constraints",
    "project": "p04-gigabit",
    "prompt": "what are the key GigaBIT M1 program constraints",
    "expect_present": [
      "--- Trusted Project State ---",
      "Zerodur",
      "1.2"
    ],
    "expect_absent": [
      "polisher suite"
    ],
    "notes": "Key constraints are in Trusted Project State (key_constraints) and in the mission-framing memory"
  },
  {
    "name": "p05-configuration",
    "project": "p05-interferometer",
    "prompt": "what is the selected interferometer configuration",
    "expect_present": [
      "folded-beam",
      "CGH"
    ],
    "expect_absent": [
      "Option B",
      "conical back",
      "polisher suite"
    ],
    "notes": "P05 architecture memory covers folded-beam + CGH. GigaBIT M1 is the mirror under test and legitimately appears in p05 source docs (the interferometer measures it), so we only flag genuinely p04-only decisions like the mirror architecture choice."
  },
  {
    "name": "p05-vendor-signal",
    "project": "p05-interferometer",
    "prompt": "what is the current vendor signal for the interferometer procurement",
    "expect_present": [
      "4D",
      "Zygo"
    ],
    "expect_absent": [
      "polisher"
    ],
    "notes": "Vendor memory mentions 4D as strongest technical candidate and Zygo Verifire SV as value path"
  },
  {
    "name": "p06-suite-split",
    "project": "p06-polisher",
    "prompt": "how is the polisher software suite split across layers",
    "expect_present": [
      "polisher-sim",
      "polisher-post",
      "polisher-control"
    ],
    "expect_absent": [
      "GigaBIT"
    ],
    "notes": "The three-layer split is in multiple p06 memories; check all three names surface together"
  },
  {
    "name": "p06-control-rule",
    "project": "p06-polisher",
    "prompt": "what is the polisher control design rule",
    "expect_present": [
      "interlocks"
    ],
    "expect_absent": [
      "interferometer"
    ],
    "notes": "Control design rule memory mentions interlocks and state transitions"
  }
]