Anto01
30ee857d62
The fixture asserted 'GigaBIT M1' must not appear in a p05 pack,
but GigaBIT M1 is the mirror the interferometer measures, so its
name legitimately shows up in p05 source docs (CGH test setup
diagrams, AOM design input, etc.). Flagging it as bleed was false
positive.
Replace the assertion with genuinely p04-only material: the
'Option B' / 'conical back' architecture decision and a p06 tag,
neither of which has any reason to appear in a p05 configuration
answer.
Harness now passes 6/6 against live Dalidou at 38f6e52 — the
first clean baseline. Subsequent retrieval/ranking/ingestion
changes can be measured against this run.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
87 lines
2.5 KiB
JSON
87 lines
2.5 KiB
JSON
[
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{
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"name": "p04-architecture-decision",
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"project": "p04-gigabit",
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"prompt": "what mirror architecture was selected for GigaBIT M1 and why",
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"expect_present": [
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"--- Trusted Project State ---",
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"Option B",
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"conical",
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"--- Project Memories ---"
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],
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"expect_absent": [
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"p06-polisher",
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"folded-beam"
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],
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"notes": "Canonical p04 decision — should surface both Trusted Project State (selected_mirror_architecture) and the project-memory band with the Option B memory"
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},
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{
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"name": "p04-constraints",
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"project": "p04-gigabit",
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"prompt": "what are the key GigaBIT M1 program constraints",
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"expect_present": [
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"--- Trusted Project State ---",
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"Zerodur",
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"1.2"
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],
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"expect_absent": [
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"polisher suite"
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],
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"notes": "Key constraints are in Trusted Project State (key_constraints) and in the mission-framing memory"
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},
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{
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"name": "p05-configuration",
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"project": "p05-interferometer",
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"prompt": "what is the selected interferometer configuration",
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"expect_present": [
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"folded-beam",
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"CGH"
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],
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"expect_absent": [
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"Option B",
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"conical back",
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"polisher suite"
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],
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"notes": "P05 architecture memory covers folded-beam + CGH. GigaBIT M1 is the mirror under test and legitimately appears in p05 source docs (the interferometer measures it), so we only flag genuinely p04-only decisions like the mirror architecture choice."
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},
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{
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"name": "p05-vendor-signal",
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"project": "p05-interferometer",
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"prompt": "what is the current vendor signal for the interferometer procurement",
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"expect_present": [
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"4D",
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"Zygo"
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],
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"expect_absent": [
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"polisher"
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],
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"notes": "Vendor memory mentions 4D as strongest technical candidate and Zygo Verifire SV as value path"
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},
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{
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"name": "p06-suite-split",
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"project": "p06-polisher",
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"prompt": "how is the polisher software suite split across layers",
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"expect_present": [
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"polisher-sim",
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"polisher-post",
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"polisher-control"
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],
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"expect_absent": [
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"GigaBIT"
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],
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"notes": "The three-layer split is in multiple p06 memories; check all three names surface together"
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},
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{
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"name": "p06-control-rule",
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"project": "p06-polisher",
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"prompt": "what is the polisher control design rule",
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"expect_present": [
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"interlocks"
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],
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"expect_absent": [
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"interferometer"
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],
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"notes": "Control design rule memory mentions interlocks and state transitions"
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}
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]
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